Sapphire wafers pave way for mass scale nanowire fabricationNovember 14th, 2007 - 2:56 am ICT by admin
Building on earlier work to grow nanowires horizontally on the surface of wafers, the team used conventional semiconductor manufacturing techniques to deposit small amounts of gold in precise locations on a sapphire wafer.
In a high-temperature process, the gold deposits bead up into nanodroplets that act as nucleation points for crystals of zinc oxide, a semiconductor.
A slight mismatch in the crystal structures of zinc oxide and sapphire induces the semiconductor to grow as a narrow nanowire in one particular direction across the wafer.
Since the starting points and the growth direction are both well known, it is relatively straightforward to add electrical contacts and other features with additional lithography steps.
The researchers used this procedure to create more than 600 nanowire-based transistors, a circuit element commonly used in digital memory chips, in a single process.
In the prototype process, they said, the nanowires typically grew in small bunches of up to eight wires at a time, but finer control over the size of the initial gold deposits made it possible to select the number of wires in each position.
They said the technique could allow industrial-scale production of nanowire-based devices.
Till now, the common approach was to grow nanowires like blades of grass on a suitable substrate, mow them off and mix them in a fluid to transfer them to a test surface, using some method to give them a preferred orientation.
When the carrier fluid dried, the nanowires were left behind like tumbled jackstraws.
Using scanning probe microscopy or similar tools, researchers hunted around for a convenient, isolated nanowire to work on, or placed electrical contacts without knowing the exact positions of the nanowires.
As such, it was not a technique suitable for mass production of nanowires. (ANI)
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Tags: circuit element, electrical contacts, gold deposits, industrial scale production, nanowires, national institute of standards and technology, nist, precise locations, preferred orientation, sapphire wafer, scanning probe microscopy, semiconductor, suitable substrate, test surface, zinc oxide