Soon, smaller and faster integrated circuits for cell phones, computers

December 20th, 2007 - 4:02 pm ICT by admin  

Washington, December 20 (ANI): Researchers at the University of California, Los Angeles have achieved success in improving integrated circuits, which are known to be the brain in computers, cell phones, DVD players, iPhones, personal digital assistants, automobiles’ navigation systems and anti-lock brakes, and many other electronic devices.

The researchers say that their success is not down to costly improvements in manufacturing but because of improved computer-aided design software based on better mathematical algorithms.

“We can get circuits designed with 30 percent less wire length using improved optimisation than what we had demonstrated three years ago, based on circuits that were samples from industry. We believe that when you apply these methods to current industry circuits, you will see similar gains. Industry says even 5 percent is very significant,” said Jason Cong, UCLA professor and chair of computer science.

“We are showing there is another way to make major improvements, with better design and better architecture,” added Cong, who has collaborated for nearly a decade with Tony Chan, UCLA professor of mathematics and the National Science Foundation’s assistant director for mathematics and physical sciences.

Traditionally, faster integrated circuits, also known as silicon chips, are made by building smaller and smaller transistors and thinner wires.

The researchers admit that the computer industry has made smaller, improved devices. They, however, insist that they are improving the design of the chip itself.

Cong, who is also a member of the California NanoSystems Institute at UCLA, has revealed that one of the goals of the collaboration is the development of silicon chips that are faster and cheaper and consume less power than the current generation of chips.

“We think optimizing chip design is an exciting direction,” he said.

Integrated circuits have a series of interconnected, nanosize nodes, the location of which on the chips surface are very important as they can minimize the wire length on which the signal travels.

Nodes include tiny “logic gates” as well as much larger memory blocks and other functional blocks.

“We have found there is a huge amount of room for improvement in the physical design of the chip itself, including where nodes are placed. We want to minimize the wire length in each node,” said UCLA mathematics graduate student Eric Radke.

Cong said that a challenge was “how do you place the nodes on a two-dimensional surface with big pieces and small pieces that are all connected to one another.”

He added: It’s like a jigsaw puzzle with millions of pieces. How do you place them to minimize the total interconnections (wires) among them.

Radke said: “It’s fairly easy to model this problem mathematically. You can think of the nodes as points on a giant graph, and you can think of the interconnects as hyper-edges that connect more than two nodes. We can use mathematics to determine how the placement problem should be solved. We use a mathematical technique called multiscale methods, in which we group nodes together until we get a mathematical problem that is small enough to solve.”

Chan and Radke design algorithms for computer software to improve the placement of the nodes and are using differential equations that they build into the algorithms. They believe that their research will lead to improved software for enhanced chip design.

The researchers have found strong evidence that existing computer-aided programs for integrated circuit designs are far from optimal. They are now working to minimize the amount of time it takes a signal to get through a processor. (ANI)

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